The main objectives of this course are:
(a) to learn the Verilog HDL hardware description language,
(b) to use Verilog for the design of synthesizable digital circuits and
(c) to familiarize students with simulation environments for digital circuits/systems specified in the Verilog HDL.
Course contents
Introduction to the Verilog HDL hardware description language.
Sequential and concurrent descriptions.
Advanced features of Verilog HDL (UDPs, transistor-level modeling).
Description of parameterized designs.
Coding guidelines for logic synthesis.
Testbenches and simulation-based circuit behavior validation.
Finite-state machines.
Non-programmable processors and the finite-state machine with datapath (FSMD) model of computation.
Parameterized designs.
Describing programmable processors in Verilog HDL.