Teaching in academia

Course objectives

The main objective of this course is to familiarize the student with the VHDL hardware description language and its use in digital circuit design. At the end of the course the student should:
(a) be able to design digital circuits in VHDL,
(b) be aware of techniques for designing digital system components such as control units, datapaths and memory resources, and
(c) to verify the proper functioning of synthesizable, synchronous, circuit descriptions in VHDL.

Course contents

  1. Introduction to the VHDL hardware description language.

  2. Elements of the VHDL language such as entity, architecture, component, package, function, procedure, generate. Sequential and concurrent descriptions.

  3. Advanced features of VHDL.

  4. Parameterized designs.

  5. Coding guidelines for logic synthesis.

  6. Testbenches.

  7. Finite-state machines.

  8. Non-programmable processors and the finite-state machine with datapath (FSMD).

  9. Parameterized designs.

  10. Describing programmable processors in VHDL.

  11. Advanced design techniques.

Course agenda (pdf)

Suggested bibliography on VHDL (pdf)

Lecture notes and corresponding code packs

Suggested projects/assignments
  • P1: Binary logarithm computation (pdf)

  • P2: Computing the minimum number of coins/banknotes for an amount (pdf)

  • P3: Processor for graph manipulation (pdf)

  • P4: Float-to-half and half-to-float conversions (pdf)

  • P5: Integer square root approximation circuit (pdf)

  • P6: Raster-scan and row-prime address generator (pdf)

  • P7: Spiral address generator (pdf)

  • P8: Turtle graphics processor (pdf)

Past exams
  • Spring 2009 exams (pdf)

  • Fall 2009 exams (pdf)

  • Winter 2010 exams (pdf)

Updated by
Nikolaos Kavvadias on February 06, 2011