Retargetable compilers

  • The CGEN (Cpu tools GENerator) project. CGEN aims to provide a framework and toolkit for writing cpu tools. It has been used for various assembler/simulator ports as for the openRISC family of processors.

  • The LLVM compilation infrastructure. Contemporary optimizing compilation infrastructure. Comes with C/C++/Objective-C frontends and numerous backends. Now at version 3.3.

  • The GCC compiler. Supports an enormous number of host/target configurations. Now at version 4.8.1.

  • The LCC compiler is a lightweight C compiler. It comes with Alpha, SPARC, MIPS and x86 backends but I have also seen 68000, Mark-1, ARM7 (maybe not any more), and XR16 backends.

  • SUIF is a research-oriented retargetable compiler. Usually used as the frontend. There exist two generations of SUIF compilers with SUIF1 being more complete and SUIF2 only being actively supported.

  • Machine SUIF is an extensible infrastructure for constructing compiler backends along with their optimization and analysis passes. What I like the most is its modular approach, where you can experiment with different combinations and ordering of compiler passes. Comes with x86, Itanium, Alpha backends. It seems to me that SUIF2-style MIPS and SPARC backends are certainly missing (a MIPS backend was included in MachSUIF-1.3.0 as well as a SPARC for SUIF1, the latter by some research group I think). Current version is machsuif- Requires a working suif- installation.

  • Valen-C compiler is a compiler for a variable-length C superset. It seems very easily retargetable but unfortunately I haven't compiled this yet in any of my Linux boxes (Mandrake 7.1, 8.0 with gcc-2.95.2, gcc-2.96, egcs-1.1.2). I suppose it may compile under Solaris and an older gcc. Requires a suif-1.1.2 installation.

  • PROMIS is an extensible parallelizing compiler architecture for hierarchical systems. It targets VLIW, superscalar and multithreaded platforms. It has a nice and intuitive GUI which however carries a lot of alpha-bugs. It is a promising work.

  • MLRISC is a framework for retargetable and optimizing compiler backends written in Standard-ML. It has a significant number of backends.

  • The Trimaran compiler research infrastructure for instruction level parallelism includes the IMPACT compiler. It also includes a simulator for the HPL-PD (PlayDoh) research architecture that follows the EPIC (Explicitly Parallel Instruction Computing) paradigm. It seems a very complete and mature work.

  • The MIRV SimpleScalar/PISA compiler target the Portable ISA architecture which is based on MIPS R2000 and is used in the SimpleScalar suite of simulators.

  • The LANCE C compiler compiles ANSI/C90 to a low-level C subset called IR-C.

Updated by
Nikolaos Kavvadias on June 22, 2013 (first version: 2003)