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loopgen

The loopgen IP collection provides fast hardware architectures for implementing nested loop structures.

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$259.99

The LOOPGEN IP collection provides fast hardware architectures for implementing nested loop structures. The collection comprises of three different architectures (variants), namely: HWLU, a mixed-level structural/RTL architecture, IXGENB, a behavioral-level and   IXGENR, a high-performance, pure RTL description of a more generalized form of the architecture.

Hardware looping architectures have potential uses for data-intensive processing in embedded systems. The implemented architectures are able to execute perfect loop nests without any cycle overhead for updating the iteration vector. Actually,  successive last iterations of nested loops are collapsed in a single cycle.

For more details on the capabilities of the loopgen IPs, please read the corresponding product brief and the README file of the distribution. loopgen is available as a source release with FREE unlimited support.

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