bstest user manual

Title bstest-s3ansk (Buttons and switches test)
Author Nikolaos Kavvadias (C) 2014
Release Date 09 June 2014
Version 1.0.0
Rev. history  


Initial release for the Spartan-3E Starter kit board.

1. Introduction

bstest is a very simple design for testing push buttons, slide switches and discrete LEDs available on the Spartan-3AN Starter Kit board by Xilinx Inc.

2. File listing

The bstest distribution includes the following files:

/bstest-s3ansk Top-level directory
AUTHORS List of authors.
COPYING 3-clause modified BSD license.
README This file.
README.html HTML version of README.
README.pdf PDF version of README.
bstest.ucf User Constraints File for the XC3S700AN-FGG484-4 device.
bstest.vhd The top-level RTL VHDL design file. Bash shell script for synthesizing the bstest design with Xilinx ISE.
impact_s3ansk.bat Windows Batch file for automatically invoking Xilinx Impact in order to download the generated bitstream to the target hardware. Bash script for generating the HTML and PDF versions. Standard Makefile for command-line usage of ISE.

3. Usage

The bstest distribution includes scripts for logic synthesis automation supporting Xilinx ISE. The corresponding synthesis script can be edited in order to specify the following for adapting to the user's setup:

3.1. Running the synthesis script

For running the Xilinx ISE synthesis tool, generating FPGA configuration bistream and downloading to the target device, execute the corresponding script from within the bstest-s3ansk directory:

$ ./

In order to successfully run the entire process, you should have the target board connected to the host and it should be powered on.

The synthesis procedure invokes several Xilinx ISE command-line tools for logic synthesis as described in the corresponding Makefile, found in the the bstest-s3ansk directory.

Typically, this process includes the following:

  • Generation of the *.xst synthesis script file.
  • Generation of the *.ngc gate-level netlist file in NGC format.
  • Building the corresponding *.ngd file.
  • Performing mapping using map which generates the corresponding *.ncd file.
  • Place-and-routing using par which updates the corresponding *.ncd file.
  • Tracing critical paths using trce for reoptimizing the *.ncd file.
  • Bitstream generation (*.bit) using bitgen, however with unused pins.

As a result of this process, the bstest.bit bitstream file is produced.

Then, the shell script invokes the Xilinx IMPACT tool by a Windows batch file, automatically passing a series of commands that are necessary for configuring the target FPGA device:

  1. Set mode to binary scan.
setMode -bs
  1. Set cable port detection to auto (tests various ports).
setCable -p auto
  1. Identify parts and their order in the scan chain.
  1. Assign the bitstream to the first part in the scan chain.
assignFile -p 1 -file bstest.bit
  1. Program the selected device.
program -p 1 -onlyFpga
  1. Exit IMPACT.

4. Prerequisities