March 19, 2015; my lovely desk at Silexica's office. |
[UPDATED: 2015-01-08] I work at Silexica Software Solutions GmbH as an R&D Engineer. |
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loopgen: VHDL IP cores for implementing nested loop structures (HTML) (PDF) (Product brief) |
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xmodz: Fast hardware implementations of integer modulo (HTML) (PDF) (Product brief) |
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llvmparse: Portable, standalone, parsers for the textual LLVM IR (HTML) (PDF) |
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mprfgen: Multi-port register file generator (HTML) (PDF) |
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aprof: Intermediate language profiler and resource utilization estimation tool (HTML) (PDF) |
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hlo: C-to-C source code optimizer (HTML) (PDF) |
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fxpemu: Fixed-point emulation library for ANSI C (HTML) (PDF) |
| fixed extensions: VHDL fixed-point arithmetic extensions package (HTML ) (PDF) (github repository) |
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ratpack: Rational arithmetic package for VHDL (HTML) (PDF) (OpenCores repository) |
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kdiv: C and assembly code generators for integer division by constant (HTML) (PDF) (Sourceforge repository) |
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kmul: C and assembly code generators for integer multiplication by constant (HTML) (PDF) (Sourceforge repository) |
| libpnmio: C library for reading and writing ASCII and binary PNM (PBM, PGM, PPM) and PFM (Portable Float Map) image files (HTML) (PDF) |
| kvcordic: Synthesizable VHDL IP core for a universal, multi-mode CORDIC computer (HTML) (PDF) (OpenCores repository) |
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complexpack: VHDL package for complex arithmetic (HTML) (PDF) |
| palutils: Palette utilities for low-level image manipulation (HTML) (PDF) |
| bbcount: Basic block annotation pass for the Machine-SUIF compiler (HTML) (PDF) |
| instrmix: Instruction mix report generator for the Machine-SUIF compiler (HTML) (PDF) |
| loopstr: Natural loop analysis pass for the Machine-SUIF compiler (HTML) (PDF) |
| liveanalysis: Liveness analysis report generator for the Machine-SUIF compiler (HTML) (PDF) |
| xopreplace: Machine-SUIF pass for replacing a function call by a SUIFvm operator (HTML) (PDF) |
| bbpart: CDFG extraction pass for the Machine-SUIF compiler (older version) (HTML) (PDF) |
| tcfggen: Task control flow graph (TCFG) extraction pass for the Machine-SUIF compiler (HTML) (PDF) |
| zolcgen: Zero-overhead loop controller code generation pass for SALTO (HTML) (PDF) |
| rasm: Retargetable assembler (HTML) (PDF) |
| digikaleid: Digital kaleidoscope using 2D cellular automata (PDF in ENG) (PDF in GRE). The digital kaleidoscope was exhibited at the 2nd Panhellenic meeting on New Technologies and Robotics. Download the bitstream and the MCS ROM file for the Xilinx Spartan-3AN starter kit board. |
| bstest: Buttons and switches tester for the Xilinx Spartan-3E (bstest-s3esk.zip) and Spartan-3AN (bstest-s3ansk.zip) starter kits (HTML for S3ESK) (PDF for S3ESK) (HTML for S3ANSK) (PDF for S3ANSK) |
| ledramp: LED ramp effect for the Xilinx Spartan-3E (ledramp-s3esk.zip) and Spartan-3AN (ledramp-s3ansk.zip) starter kits (HTML for S3ESK) (PDF for S3ESK) (HTML for S3ANSK) (PDF for S3ANSK) |
| color_maker: A color picker as a VGA tester for the Xilinx Spartan-3E (color_maker-s3esk.zip) and Spartan-3AN (color_maker-s3ansk.zip) starter kits (HTML for S3ESK) (PDF for S3ESK) (HTML for S3ANSK) (PDF for S3ANSK) |
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image_processing_examples (ipe): Image processing primitives for reading and writing PNM files in VHDL testbenches (HTML) (PDF). This is a fork of Martin J. Thompson's image_processing_examples |
| elemapprox: Approximating and plotting elementary functions as ASCII or bitmap (PBM) for ANSI C, Verilog HDL and VHDL (HTML) (PDF) |
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interval: Interval arithmetic API for ANSI C (HTML) (PDF) |
| oberon00: Oberon-0 subset for use as a hardware-software description language (HTML) (PDF) |
| gvizparse: Standalone lex/yacc parser for the Graphviz format (HTML) (PDF) |
| pde2hw: FPGA-based hardware prototypes in Processing (HTML) (PDF) |
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dlx: DLX functional model for ArchC (HTML) (PDF) |
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toy: Assembler and simulator for the Princeton TOY machine (HTML) (PDF) (Princeton TOY website) |
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toysim: ArchC functional simulator for the Princeton TOY machine (HTML) (PDF) |
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[UPDATED] mu0: HDL models and programming tools for the educational MU0 processor (HTML) (PDF) (Prof. G. Constantinides-Architecture-Lecture 2-A very simple processor) (Assembler and debugger/simulator by benjya) (Pete Jinks-MU0-A Simple Computer) (James Bedford-Understanding the MU0 Processor) |
| [NEW] rasalghul: The RASter ALGorithms HULk |
Nikolaos Kavvadias is the coinventor of the ZOLC (Zero-Overhead Loop Controller) technique (with Prof. Spiridon Nikolaidis). The ZOLC technique is used for eliminating looping overhead operations in either FSM-based, non-programmable, architectures as well as modern pipelined microprocessors.
N. Kavvadias and S. Nikolaidis, "Elimination of overhead operations in complex loop structures for embedded microprocessors," IEEE Transactions on Computers, Vol. 57, No. 2, pp. 200-214, February 2008. (DOI article link) (bibtex) has been cited by: